Metadata-Version: 2.1
Name: svmodule
Version: 1.1.2
Summary: [System]Verilog Module I/O parser and printer
Home-page: https://github.com/cclienti/svmodule
Author: Christophe Clienti
Author-email: cclienti@wavecruncher.net
License: GPL-3.0
Description: # SVModule
        
        ## Introduction
        SVModule is set of python scripts/classes to parse a [System]Verilog module declaration and paste it as an instance,
        parameter definitions... It manages module imports, parameters, standard and interface I/O ports.
        
        The objective is to provide a similar behavior of the emacs VHDL mode but in the form of shell commands. Then it is
        easy to wrap them into your preferred editor as macros or functions.
        
        ## License
        SVModule is distributed under the GPLv3, the complete license description can be found
        [here](http://www.gnu.org/licenses/gpl-3.0.html).
        
        ## General information
        The documentation is available [here](https://wavecruncher.net/svmodule). Of course, contribution are welcomed.
        
Platform: UNKNOWN
Classifier: Programming Language :: Python :: 3
Classifier: License :: OSI Approved :: GNU General Public License v3 (GPLv3)
Classifier: Operating System :: OS Independent
Classifier: Development Status :: 5 - Production/Stable
Classifier: Environment :: Console
Classifier: Intended Audience :: Developers
Description-Content-Type: text/markdown
