package require -exact qsys 14.0


# 
# module {{ ipname }}
# 
set_module_property DESCRIPTION ""
set_module_property NAME {{ ipname }}
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP ipgen_ipcores
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME {{ ipname }}
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL {{ ipname }}
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file "./implementation/{{ hdlname }}" VERILOG PATH {{ hdlname }} TOP_LEVEL_FILE
#add_fileset_file "./implementation/{{ common_hdlname }}" VERILOG PATH {{ common_hdlname }}


# 
# parameters
# 
{%- for param in tcl_parameters | sort(attribute=0) %}
add_parameter {{ param[0] }} {{ param[2] }} {{ param[1] }} 
set_parameter_property {{ param[0] }} DEFAULT_VALUE {{ param[1] }} 
set_parameter_property {{ param[0] }} DISPLAY_NAME {{ param[0] }} 
set_parameter_property {{ param[0] }} TYPE {{ param[2] }} 
set_parameter_property {{ param[0] }} UNITS None
{%- if param[2] == 'STD_LOGIC_VECTOR' %}
set_parameter_property {{ param[0] }} ALLOWED_RANGES 0:17179869183
{%- endif %}
set_parameter_property {{ param[0] }} HDL_PARAMETER false
{%- endfor %}


# 
# display items
# 
{%- for master in masterlist | sort(attribute='name') %}
# 
# connection point {{ master.name }}
# 
add_interface {{ master.name }} avalon start
set_interface_property {{ master.name }} addressUnits SYMBOLS
{%- if not single_clock %}
set_interface_property {{ master.name }} associatedClock sys_{{ master.name }}
set_interface_property {{ master.name }} associatedReset sys_{{ master.name }}_reset
{%- else %}
set_interface_property {{ master.name }} associatedClock sys_user
set_interface_property {{ master.name }} associatedReset sys_user_reset
{%- endif %}
set_interface_property {{ master.name }} bitsPerSymbol 8
{%- if master.lite %}
set_interface_property {{ master.name }} burstOnBurstBoundariesOnly true
{%- else %}
set_interface_property {{ master.name }} burstOnBurstBoundariesOnly false
{%- endif %}
set_interface_property {{ master.name }} burstcountUnits WORDS
set_interface_property {{ master.name }} doStreamReads false
set_interface_property {{ master.name }} doStreamWrites false
set_interface_property {{ master.name }} holdTime 0
set_interface_property {{ master.name }} linewrapBursts false
set_interface_property {{ master.name }} maximumPendingReadTransactions 256
set_interface_property {{ master.name }} maximumPendingWriteTransactions 0
set_interface_property {{ master.name }} readLatency 0
set_interface_property {{ master.name }} readWaitTime 1
set_interface_property {{ master.name }} setupTime 0
set_interface_property {{ master.name }} timingUnits Cycles
set_interface_property {{ master.name }} writeWaitTime 0
set_interface_property {{ master.name }} ENABLED true
set_interface_property {{ master.name }} EXPORT_OF ""
set_interface_property {{ master.name }} PORT_NAME_MAP ""
set_interface_property {{ master.name }} CMSIS_SVD_VARIABLES ""
set_interface_property {{ master.name }} SVD_ADDRESS_GROUP ""

add_interface_port {{ master.name }} avm_{{ master.name }}_address address Output {{ ext_addrwidth }}
add_interface_port {{ master.name }} avm_{{ master.name }}_waitrequest waitrequest Input 1
add_interface_port {{ master.name }} avm_{{ master.name }}_byteenable byteenable Output {{ int(master.datawidth / 8) }}
{%- if not master.lite %}
add_interface_port {{ master.name }} avm_{{ master.name }}_burstcount burstcount Output 9
{%- endif %}
add_interface_port {{ master.name }} avm_{{ master.name }}_read read Output 1
add_interface_port {{ master.name }} avm_{{ master.name }}_readdata readdata Input {{ master.datawidth }}
add_interface_port {{ master.name }} avm_{{ master.name }}_readdatavalid readdatavalid Input 1
add_interface_port {{ master.name }} avm_{{ master.name }}_write write Output 1
add_interface_port {{ master.name }} avm_{{ master.name }}_writedata writedata Output {{ master.datawidth }}
{% endfor %}


{% for slave in slavelist | sort(attribute='name') %}
# 
# connection point {{ slave.name }}
# 
add_interface {{ slave.name }} avalon end
set_interface_property {{ slave.name }} addressUnits WORDS
{%- if not single_clock %}
set_interface_property {{ slave.name }} associatedClock sys_{{ slave.name }}
set_interface_property {{ slave.name }} associatedReset sys_{{ slave.name }}_reset
{%- else %}
set_interface_property {{ slave.name }} associatedClock sys_user
set_interface_property {{ slave.name }} associatedReset sys_user_reset
{%- endif %}
set_interface_property {{ slave.name }} bitsPerSymbol 8
{%- if slave.lite %}
set_interface_property {{ slave.name }} burstOnBurstBoundariesOnly true
{%- else %}
set_interface_property {{ slave.name }} burstOnBurstBoundariesOnly false
{%- endif %}
set_interface_property {{ slave.name }} burstcountUnits WORDS
set_interface_property {{ slave.name }} explicitAddressSpan 0
set_interface_property {{ slave.name }} holdTime 0
set_interface_property {{ slave.name }} linewrapBursts false
set_interface_property {{ slave.name }} maximumPendingReadTransactions 1
set_interface_property {{ slave.name }} maximumPendingWriteTransactions 0
set_interface_property {{ slave.name }} readLatency 0
set_interface_property {{ slave.name }} readWaitTime 1
set_interface_property {{ slave.name }} setupTime 0
set_interface_property {{ slave.name }} timingUnits Cycles
set_interface_property {{ slave.name }} writeWaitTime 0
set_interface_property {{ slave.name }} ENABLED true
set_interface_property {{ slave.name }} EXPORT_OF ""
set_interface_property {{ slave.name }} PORT_NAME_MAP ""
set_interface_property {{ slave.name }} CMSIS_SVD_VARIABLES ""
set_interface_property {{ slave.name }} SVD_ADDRESS_GROUP ""

add_interface_port {{ slave.name }} avs_{{ slave.name }}_address address Input 1
add_interface_port {{ slave.name }} avs_{{ slave.name }}_waitrequest waitrequest Output 1
add_interface_port {{ slave.name }} avs_{{ slave.name }}_byteenable byteenable Input {{ int(slave.datawidth / 8) }}
{%- if not slave.lite %}
add_interface_port {{ slave.name }} avm_{{ slave.name }}_burstcount burstcount Output 9
{%- endif %}
add_interface_port {{ slave.name }} avs_{{ slave.name }}_read read Input 1
add_interface_port {{ slave.name }} avs_{{ slave.name }}_readdata readdata Output {{ slave.datawidth }}
add_interface_port {{ slave.name }} avs_{{ slave.name }}_readdatavalid readdatavalid Output 1
add_interface_port {{ slave.name }} avs_{{ slave.name }}_write write Input 1
add_interface_port {{ slave.name }} avs_{{ slave.name }}_writedata writedata Input {{ slave.datawidth }}
set_interface_assignment {{ slave.name }} embeddedsw.configuration.isFlash 0
set_interface_assignment {{ slave.name }} embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment {{ slave.name }} embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment {{ slave.name }} embeddedsw.configuration.isPrintableDevice 0
{% endfor %}


{% if len(tcl_ports) > 0 %}
# 
# connection point conduit_end_0
# 
add_interface conduit_end_0 conduit end
set_interface_property conduit_end_0 associatedClock ""
set_interface_property conduit_end_0 associatedReset ""
set_interface_property conduit_end_0 ENABLED true
set_interface_property conduit_end_0 EXPORT_OF ""
set_interface_property conduit_end_0 PORT_NAME_MAP ""
set_interface_property conduit_end_0 CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end_0 SVD_ADDRESS_GROUP ""
{%- endif %}
{%- for port in tcl_ports | sort(attribute=0) %}
add_interface_port conduit_end_0 {{ port[0] }} {{ ipname }}_{{ port[0] }} {{ port[1] }} {{ port[2] }}
{% endfor %}


# 
# connection point sys_user
# 
add_interface sys_user clock end
set_interface_property sys_user clockRate 0
set_interface_property sys_user ENABLED true
set_interface_property sys_user EXPORT_OF ""
set_interface_property sys_user PORT_NAME_MAP ""
set_interface_property sys_user CMSIS_SVD_VARIABLES ""
set_interface_property sys_user SVD_ADDRESS_GROUP ""

add_interface_port sys_user csi_sys_user_clk clk Input 1


# 
# connection point sys_user_reset
# 
add_interface sys_user_reset reset end
set_interface_property sys_user_reset associatedClock sys_user
set_interface_property sys_user_reset synchronousEdges DEASSERT
set_interface_property sys_user_reset ENABLED true
set_interface_property sys_user_reset EXPORT_OF ""
set_interface_property sys_user_reset PORT_NAME_MAP ""
set_interface_property sys_user_reset CMSIS_SVD_VARIABLES ""
set_interface_property sys_user_reset SVD_ADDRESS_GROUP ""

add_interface_port sys_user_reset csi_sys_user_reset_n reset_n Input 1

