Metadata-Version: 2.1
Name: pySVModel
Version: 0.3.0
Summary: An abstract SystemVerilog language model (incl. Verilog).
Home-page: https://github.com/edaa-org/pySVModel
Author: Patrick Lehmann
Author-email: Paebbels@gmail.com
License: Apache 2.0
Project-URL: Documentation, https://edaa-org.github.io/pySVModel
Project-URL: Source Code, https://github.com/edaa-org/pySVModel
Project-URL: Issue Tracker, https://github.com/edaa-org/pySVModel/issues
Keywords: Python3 Verilog SystemVerilog Language Model Abstract
Platform: UNKNOWN
Classifier: License :: OSI Approved :: Apache Software License
Classifier: Operating System :: OS Independent
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Programming Language :: Python :: 3.6
Classifier: Programming Language :: Python :: 3.7
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Development Status :: 3 - Alpha
Classifier: Intended Audience :: Developers
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Topic :: Software Development :: Code Generators
Classifier: Topic :: Software Development :: Compilers
Classifier: Topic :: Utilities
Requires-Python: >=3.6
Description-Content-Type: text/markdown
License-File: LICENSE.md

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An abstract language model of SystemVerilog (incl. Verilog) written in Python.

<p align="center">
  <a title="edaa-org.github.io/pySVModel" href="https://edaa-org.github.io/pySVModel"><img width="500px" src="doc/_static/banner.svg"/></a>
</p>


## Main Goals

This package provides a unified abstract language model for SystemVerilog (incl. Verilog).
Projects reading from source files can derive own classes and implement additional logic to create a concrete language
model for their tools.

Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features
and services on such a model, while supporting multiple frontends.


## Use Cases

### pySVModel Generators

*TBD*

### pySVModel Consumers

*TBD*

## Examples

### List all Modules with Parameters and Ports

*TBD*

## Contributors

* [Patrick Lehmann](https://github.com/Paebbels) (Maintainer)
* [Unai Martinez-Corral](https://github.com/umarcor)
* [and more...](https://github.com/edaa-org/pySVModel/graphs/contributors)

## License

This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).  
The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).

-------------------------
SPDX-License-Identifier: Apache-2.0


