Metadata-Version: 1.0
Name: uart
Version: 0.3.5
Summary: Utility for simply creating and modifying VHDL bus slave modules
Home-page: http://github.com/olagrottvik/art
Author: Ola Groettvik
Author-email: olagrottvik@gmail.com
License: MIT
Description-Content-Type: UNKNOWN
Description: b"# uart register tool\n\n. uart does not refer to the hardware device!\n\n## Concept\n\nThe main goal of the project is to able to automatically create and modify VHLD bus slave modules based on a simple definition format. By employing VHDL records the handling of the registers can be completely hidden in a module seperate from the rest of the designers logic. All referring to the registers are done via a record which specifies if the register is read-only or read-write, and also includes the name. All bus-specific signals are also wrapped in records. This increases the readability of the design as a whole.\n\n## Bus support\n\nuart currently supports these bus-types:\n\n- AXI4-lite\n  \n\n## Getting Started\n\n`pip install uart`\n\n\n### Usage\n\n`uart.py FILE [-o DIR]`\n\n`uart.py -c FILE [-o DIR]`\n\n`uart.py -e FILE [-o DIR]`\n\n`uart.py --version`\n\n`uart.py -h | --help`\n  \n\n### Examples\n\nThe examples folder contain a JSON-file generated by the menu-system. This file is readable to the point that you can create your own from this template alone if you can't bothered with the menu-system. The folder also contain the output files generated based on the JSON-file.\n\n\n## Contributing\n\nIf you have ideas on how to improve the project, please review [CONTRIBUTING.md](CONTRIBUTING.md) for details. Note that we also have a [Code of Conduct](CODE_OF_CONDUCT.md). \n\n\n## License\n\nThis project is licensed under the MIT license - see [LICENSE](LICENSE) for details.\n\n"
Keywords: vhdl,bus,axi
Platform: UNKNOWN
