LICENCE
MANIFEST.in
README.md
pyproject.toml
requirements.txt
setup.cfg
src/cbadc/__init__.py
src/cbadc/__version__.py
src/cbadc/analog_frontend.py
src/cbadc/fom.py
src/cbadc/utilities.py
src/cbadc.egg-info/PKG-INFO
src/cbadc.egg-info/SOURCES.txt
src/cbadc.egg-info/dependency_links.txt
src/cbadc.egg-info/requires.txt
src/cbadc.egg-info/top_level.txt
src/cbadc.egg-info/zip-safe
src/cbadc/analog_signal/__init__.py
src/cbadc/analog_signal/_analog_signal.py
src/cbadc/analog_signal/clock.py
src/cbadc/analog_signal/constant_signal.py
src/cbadc/analog_signal/impulse_responses.py
src/cbadc/analog_signal/quadrature.py
src/cbadc/analog_signal/ramp.py
src/cbadc/analog_signal/sinc_pulse.py
src/cbadc/analog_signal/sinusoidal.py
src/cbadc/analog_signal/zero_order_hold.py
src/cbadc/analog_system/__init__.py
src/cbadc/analog_system/analog_system.py
src/cbadc/analog_system/chain_of_integrators.py
src/cbadc/analog_system/filters.py
src/cbadc/analog_system/leap_frog.py
src/cbadc/analog_system/modulator.py
src/cbadc/analog_system/topology.py
src/cbadc/circuit/__init__.py
src/cbadc/circuit/analog_frontend.py
src/cbadc/circuit/digital_control.py
src/cbadc/circuit/lc_tank.py
src/cbadc/circuit/opamp.py
src/cbadc/circuit/ota.py
src/cbadc/circuit/simulator.py
src/cbadc/circuit/state_space.py
src/cbadc/circuit/testbench.py
src/cbadc/circuit/components/__init__.py
src/cbadc/circuit/components/analog_delay.py
src/cbadc/circuit/components/comparator.py
src/cbadc/circuit/components/integrator.py
src/cbadc/circuit/components/observer.py
src/cbadc/circuit/components/opamp.py
src/cbadc/circuit/components/ota.py
src/cbadc/circuit/components/passives.py
src/cbadc/circuit/components/reference_source.py
src/cbadc/circuit/components/sources.py
src/cbadc/circuit/components/summer.py
src/cbadc/circuit/components/vcvs.py
src/cbadc/circuit/components/voltage_buffer.py
src/cbadc/circuit/models/__init__.py
src/cbadc/circuit/models/analog_delay.py
src/cbadc/circuit/models/comparator.py
src/cbadc/circuit/models/integrator.py
src/cbadc/circuit/models/observer.py
src/cbadc/circuit/models/ota.py
src/cbadc/circuit/models/reference_source.py
src/cbadc/circuit/models/summer.py
src/cbadc/circuit/models/vcvs.py
src/cbadc/circuit/models/voltage_buffer.py
src/cbadc/circuit/templates/__init__.py
src/cbadc/circuit/templates/comment.cir.j2
src/cbadc/circuit/templates/preamble.txt.j2
src/cbadc/circuit/templates/testbench.cir.j2
src/cbadc/circuit/templates/testbench_cadence.txt
src/cbadc/circuit/templates/ngspice/__init__.py
src/cbadc/circuit/templates/ngspice/capacitor.cir.j2
src/cbadc/circuit/templates/ngspice/dc_voltage_source.cir.j2
src/cbadc/circuit/templates/ngspice/inductor.cir.j2
src/cbadc/circuit/templates/ngspice/model.cir.j2
src/cbadc/circuit/templates/ngspice/ota.cir.j2
src/cbadc/circuit/templates/ngspice/pulse_voltage_source.cir.j2
src/cbadc/circuit/templates/ngspice/reference_source_model.cir.j2
src/cbadc/circuit/templates/ngspice/resistor.cir.j2
src/cbadc/circuit/templates/ngspice/simulator.cir.j2
src/cbadc/circuit/templates/ngspice/sine_voltage_source.cir.j2
src/cbadc/circuit/templates/ngspice/sub_circuit.cir.j2
src/cbadc/circuit/templates/ngspice/sub_circuit_definition.cir.j2
src/cbadc/circuit/templates/ngspice/testbench.cir.j2
src/cbadc/circuit/templates/ngspice/vcvs.cir.j2
src/cbadc/circuit/templates/ngspice/voltage_buffer.cir.j2
src/cbadc/circuit/templates/ngspice/xspice.cir.j2
src/cbadc/circuit/templates/spectre/__init__.py
src/cbadc/circuit/templates/spectre/capacitor.cir.j2
src/cbadc/circuit/templates/spectre/dc_voltage_source.cir.j2
src/cbadc/circuit/templates/spectre/inductor.cir.j2
src/cbadc/circuit/templates/spectre/pulse_voltage_source.cir.j2
src/cbadc/circuit/templates/spectre/resistor.cir.j2
src/cbadc/circuit/templates/spectre/simulator.cir.j2
src/cbadc/circuit/templates/spectre/sine_voltage_source.cir.j2
src/cbadc/circuit/templates/spectre/sub_circuit.cir.j2
src/cbadc/circuit/templates/spectre/sub_circuit_definition.cir.j2
src/cbadc/circuit/templates/spectre/testbench.cir.j2
src/cbadc/circuit/templates/spectre/verilog_ams.cir.j2
src/cbadc/circuit/templates/verilog_ams/base_module.vams.j2
src/cbadc/circuit/templates/verilog_ams/clocked_comparator.vams.j2
src/cbadc/circuit/templates/verilog_ams/integrator.vams.j2
src/cbadc/circuit/templates/verilog_ams/library.vams.j2
src/cbadc/circuit/templates/verilog_ams/module.vams.j2
src/cbadc/circuit/templates/verilog_ams/observer.vams.j2
src/cbadc/circuit/templates/verilog_ams/ota.vams.j2
src/cbadc/circuit/templates/verilog_ams/preamble.txt.j2
src/cbadc/circuit/templates/verilog_ams/summer.vams.j2
src/cbadc/circuit/templates/verilog_ams/voltage_buffer.vams.j2
src/cbadc/digital_control/__init__.py
src/cbadc/digital_control/digital_control.py
src/cbadc/digital_control/dither_control.py
src/cbadc/digital_control/multi_level_digital_control.py
src/cbadc/digital_control/switch_capacitor_control.py
src/cbadc/digital_control/utilities.py
src/cbadc/digital_estimator/__init__.py
src/cbadc/digital_estimator/_filter_coefficients.py
src/cbadc/digital_estimator/adaptive_filter.py
src/cbadc/digital_estimator/batch_estimator.py
src/cbadc/digital_estimator/fir_estimator.py
src/cbadc/digital_estimator/iir_estimator.py
src/cbadc/digital_estimator/nuv_estimator.py
src/cbadc/digital_estimator/parallel_digital_estimator.py
src/cbadc/ode_solver/__init__.py
src/cbadc/ode_solver/mpmath.py
src/cbadc/ode_solver/sympy.py
src/cbadc/simulator/__init__.py
src/cbadc/simulator/_base_simulator.py
src/cbadc/simulator/numerical_simulator.py
src/cbadc/simulator/numpy_simulator.py
src/cbadc/simulator/simulator.py
src/cbadc/simulator/utilities.py
src/cbadc/synthesis/__init__.py
src/cbadc/synthesis/chain_of_integrators.py
src/cbadc/synthesis/continuous_time_sigma_delta.py
src/cbadc/synthesis/lc_tank.py
src/cbadc/synthesis/leap_frog.py
src/cbadc/synthesis/quadrature.py